Encrypting data at rest and in transit is routine. The hard part has been the moment a processor actually works on it, when the data normally has to be decrypted in memory. Google says its newest TPU system closes that gap for AI workloads, and it brought AMD along to do it.
In a blog post Monday morning, Amin Vahdat, Google’s SVP and chief technologist for AI and infrastructure, introduced TPU 8tx and TPU 8i Max, two additions to its eighth-generation family. With TPU 8t for training and TPU 8i for reasoning introduced at Cloud Next in April, that makes four TPU systems in one year, which Vahdat said is a first for Google. He also wrote that TPUs have grown into a business with nearly 100 customers, among them frontier labs, trading firms, retailers and universities.
Google calls these systems rather than new chips. Each one rearranges the packaging, memory, networking and security around silicon it already makes.
Confidential inference, with AMD on the host side
TPU 8tx uses the same silicon as TPU 8t and is aimed at regulated enterprises and governments running frontier or proprietary models and agents against sensitive data. Google said it keeps data and model weights protected and isolated even while in use. It also borrows the low-latency Boardfly network from TPU 8i, which Google says gives it up to 2x lower latency than TPU 8t with a near-zero performance penalty. Teams can fine-tune on private data, distill models and run reinforcement learning on the same system without moving that data between clusters.
AMD said in its own announcement that 5th Gen EPYC processors serve as the host CPUs and that TPU 8tx is the first cloud TPU system with hardware-enforced confidential computing. The design uses AMD’s Secure Encrypted Virtualization to extend protection from the CPU to the attached accelerators. An accelerator’s identity and security configuration are verified before it gets direct access to protected memory, which AMD says helps keep prompts, model weights and intermediate data encrypted in CPU memory and in transit between the host and the TPUs.
“When teams move AI agents into production, they need confidence that their data and intellectual property stay private, even from the underlying infrastructure,” Mark Lohmeyer, vice president and general manager for AI and computing infrastructure at Google Cloud, said in AMD’s release. Speaking at a briefing covered by Network World, he said: “You shouldn’t have to trade off between security and performance.”
NVIDIA is courting the same buyers. It added a Confidential Bare Metal option for model builders in October, with Google Cloud among its early backers.
Two chips in one package for long contexts
TPU 8i Max goes after memory limits. Google combined two TPU 8i chips in a single package, giving it double the compute, SRAM and HBM bandwidth of TPU 8i while fitting twice the silicon into the existing rack footprint. Network World, citing Lohmeyer, reported 384 GB of high-bandwidth memory, 33% more than TPU 8i, along with 17.2 TB per second of memory bandwidth and 768 MB of on-chip SRAM.
The announcement also covered software. Google is open-sourcing TPU Sync, which tiers KV caches off the chip and syncs reinforcement-learning weights, and it says the tool cuts KV transfer latency and time to first token by more than 90%. Network World reported that it is also available for v7, v6 and v5 TPUs. Cloud Pathways and GKE dynamic slicing are now generally available, and Google says dynamic slicing makes job startup up to 5x faster and fault recovery up to 4.5x faster. A TPU agent suite in preview plugs into Claude Code, Cursor and Google Antigravity to automate onboarding and kernel tuning, building on the TorchTPU release from October.
Google’s reach with these TPUs is also widening beyond its own cloud. Oracle plans to offer TPUs on OCI starting in 2027. Vahdat’s post didn’t give pricing or availability dates for either new system. Google scheduled a broadcast on the new TPUs for 9 a.m. PT Monday.
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