IBM announced a prototype chip packing nearly 100 billion transistors into a fingernail-sized area. The design uses a new “nanostack” architecture that stacks transistors in two layers instead of shrinking them only on a flat plane. The result nearly doubles the density of the company’s 2-nanometer chip from 2021 and points to performance gains or major efficiency improvements.
Jay Gambetta, director of IBM Research, called the work “a meaningful leap forward” during a press conference. He expects nanostack-based chips to appear in data centers within a decade. Dan Hutcheson of TechInsights described the advance as “transformational” and said it adds “another 10, 15 years on the roadmap.”
The 0.7-nanometer node, also labeled 7 angstroms, marks the first public demonstration of logic technology below the 1-nanometer threshold. The name follows industry convention rather than an exact physical measurement. Transistor spacing has remained around 40 nanometers for years, according to University of Illinois professor Qing Cao.
From flat to stacked
Engineers built the prototype layer by layer. They fabricated transistors on one silicon wafer, bonded a second wafer on top, and created another transistor layer. The upper transistors sit staggered relative to the lower ones. This offset simplifies wiring and allows independent optimization of each layer’s materials.
The approach builds on IBM’s earlier nanosheet transistors. In the new design, each channel consists of three nanosheets spaced nine nanometers apart. Researchers also achieved functional CMOS inverter operation and reported 40 percent better SRAM scaling, a key gain for AI workloads that demand high on-chip memory bandwidth.
Compared with the 2-nanometer generation, the nanostack prototype projects up to 50 percent higher performance or 70 percent greater energy efficiency. IBM’s technical paper at the 2025 VLSI Symposium and follow-on SRAM results presented in 2026 detail these metrics. The company sees a path to production in roughly five years, with the architecture supporting at least another decade of scaling.
Other firms pursue similar three-dimensional ideas. Intel, Samsung, and TSMC have explored CFET structures. IBM’s staggered layout and wafer-bonding technique differ from approaches that fabricate layers separately and then bond them. Cao noted that IBM’s method enables tighter alignment on full wafers using production equipment.
Manufacturing hurdles remain. Adding layers raises defect rates because a fault in either tier ruins the chip. Thermal budgets must stay below 400 °C to protect lower-layer connections. IBM achieved the second layer at acceptable temperatures but has not disclosed the exact process. Academic groups, including Cao’s, have demonstrated even lower-temperature stacking methods as proof of concept.
Broader industry context
The announcement arrives as demand for AI accelerators strains power supplies and cooling systems. Denser, more efficient chips could ease those pressures. IBM estimates that a 7-angstrom AI accelerator might deliver around 9,000 TOPS versus roughly 1,500 TOPS from current designs, potentially shortening large-model training times from months to weeks.
Recent coverage from MIT Technology Review, Ars Technica, and Forbes highlights the same density and efficiency claims. Reuters reported the news on June 25, 2026, noting the technology’s relevance to AI computing. IBM’s own research blog and press release provide the primary technical details and quotes from Gambetta and Huiming Bu, vice president of global semiconductor R&D.
IBM has no fabrication plants of its own for leading-edge logic. It partners with foundries and equipment makers including ASML for High NA EUV tools now arriving in Albany, New York. The company also collaborates with Lam Research, Tokyo Electron, and SCREEN on process development. Production of sub-1-nanometer chips would likely involve those partners or their customers.
Analysts on X noted the research milestone while questioning timelines. One post observed that TSMC and Samsung currently ship the most advanced nodes, while IBM’s work remains at the prototype stage. Another highlighted the vertical stacking concept as a practical response to atomic-scale limits.
IBM’s roadmap projects continued progress through multiple generations of the nanostack structure. The company has long contributed foundational transistor technologies that later reached commercial fabs. Whether this particular architecture follows the same path depends on successful transfer to manufacturing partners and resolution of the thermal and yield challenges that accompany any multi-layer build.
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