AMD just gave the Linux kernel a new way to recognize a third class of CPU core. Hours ago, engineer Vishal Badole posted a patch series that extends x86 topology support to a “Low Power” core type. The change targets future AMD heterogeneous processors that will mix full-performance cores, dense efficiency cores, and these even lower-power variants.
Until now the kernel distinguished only Performance and Efficiency cores. Low Power cores get their own identifier. The patches read CPUID leaf 0x80000026 EBX[31:28]. Value 2 marks a core built for minimal consumption during background tasks or idle periods. Simple addition. A dozen lines of code propagate the type through the topology code and expose it to user space via debugfs.
Why the Kernel Needs a New Category
But the distinction matters more than it first appears. Badole explained in the cover letter that treating these cores like regular efficiency cores would break two things. First, user-space tools querying /sys/kernel/debug/x86/topo/cpus/* currently see “unknown” for them. Second, the amd_get_boost_ratio_numerator function must scale low-power cores using amd_get_highest_perf rather than a fixed CPPC ceiling. The existing efficiency-core path already follows this logic. The new type simply makes the behavior explicit and correct. (Phoronix, June 29, 2026)
The patches sit on the kernel mailing list under review. They arrive at a moment when AMD prepares more aggressive core mixing. Leaks and technical disclosures point to Zen 5-derived low-power cores that deliver 65 to 75 percent of full Zen 5 IPC while running at 50 to 60 percent of the clock speed. On a 4-nanometer node those cores stay under 1 watt each at peak efficiency. That beats Intel’s E-cores on power. The figures come from internal AMD slides shown to select partners and analyzed by industry watchers.
Notebookcheck reported the numbers in April 2025 after reviewing Moore’s Law Is Dead leaks. The low-power cores, sometimes called LP or Zen 5 LP, target integration on the I/O die of client processors such as Olympic Ridge. Those chips keep full Zen 6 cores on separate compute dies while placing the low-power units closer to memory controllers and accelerators. Same AM5 socket. Different balance. The approach echoes how AMD already mixes Zen 5 and Zen 5c cores in server silicon but pushes efficiency further for always-on background work, sensor processing, or light AI inference.
Servers follow a parallel track. SemiAnalysis detailed AMD’s Venice platform plans earlier this year. The Zen 6 generation brings dense Zen 6c cores with a full 4MB of L3 cache per core, correcting the halving seen in Zen 5c. A 256-core variant packs eight N2-process CCDs, each with 32 cores arranged in a 4×8 mesh. AMD claims the top SKU delivers over 1.7 times better performance per watt than the 192-core Turin dense part on SPECrate 2017 integer. The company also readies an 8-channel SP8 platform as successor to the low-power Siena series, supporting up to 128 dense Zen 6c cores in a smaller socket. Intel canceled its competing 8-channel design. AMD doubles down. (SemiAnalysis, February 2026)
Power efficiency sits at the center of every decision. Recent Phoronix tests of the EPYC 4545P showed 16 Zen 5 cores running comfortably inside a 65-watt envelope. Base clock drops to 3.0 GHz yet the part still supports full DDR5-5600 ECC, AVX-512, and server features. Edge deployments, industrial controllers, and dense storage nodes benefit. Those systems rarely need every cycle. They demand they stay cool and quiet. A dedicated low-power core type helps the scheduler park threads intelligently instead of guessing from frequency or cache size alone.
And the Linux changes arrive none too soon. Kernel scheduler decisions already weigh performance versus efficiency cores on Intel and AMD hybrid parts. Adding a third tier requires teaching the scheduler, thermal framework, and power-management drivers how to treat these cores differently. Vishal Badole’s series focuses on topology reporting and CPPC scaling. Follow-on patches will likely tune task placement, idle states, and frequency governors. Developers have months to refine before silicon ships in volume.
Client products stand to gain the most immediate visibility. Laptop and desktop chips could run background services, network stack, or telemetry on the low-power cores while the big cores sleep. Battery life improves. Fan noise drops. The same cores may appear in future Ryzen AI or Strix-derived parts that already blend CPU, GPU, and NPU. Early simulations suggest the LP cores land between Zen 3 and Zen 4 in absolute IPC yet sip so little power that the overall package efficiency rises.
Server roadmaps show similar thinking at scale. Dense Zen 6c already targets cloud-native workloads that favor thread count over single-thread speed. The low-power type could extend that logic to auxiliary functions inside the socket or to specialized SKUs for edge servers. AMD’s EPYC 8005 series already ships 8-to-84 Zen 5 cores in 70-to-225 watt envelopes. Future variants may mix all three core types on one package. The kernel must recognize them to avoid mis-scheduling.
Industry observers note the pattern. AMD spent years perfecting chiplet disaggregation. It now applies the same principle to core microarchitectures. One I/O die carries the low-power cores, memory interfaces, and accelerators. Separate CCDs carry the high-performance engines. Yields improve. Costs fall. Software complexity rises, but the Linux patches reduce one piece of that burden.
No public silicon exists yet with the new core type. The patches therefore remain speculative in testing. Reviewers on the mailing list will check for conflicts with existing AMD topology code, Hygon compatibility, and interactions with the amd_pstate driver. Early feedback looks positive. The change stays small. Its effect on real systems will grow as heterogeneous designs proliferate through 2026 and 2027.
Phoronix first broke the patch story this morning. Coverage elsewhere remains limited. Yet the technical press already connects the dots to earlier leaks about Olympic Ridge and Venice. The picture sharpens. AMD prepares a future where Linux sees Performance, Efficiency, and Low Power cores as first-class citizens. Schedulers will migrate threads across three distinct performance and power curves. Power budgets tighten. Core counts climb. The kernel adapts.
So the patches represent more than housekeeping. They signal AMD’s conviction that three core flavors deliver better overall efficiency than two. Hardware teams already taped out the silicon. Software teams now catch up. The result should appear in Linux 6.13 or 6.14, ready for the first wave of Zen 6 products that mix all three types in one socket. Expect quieter laptops, denser edge servers, and more granular power management. The foundation sits in those dozen lines of topology code.
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