AMD just pulled back the curtain on its long-term server CPU plans. At the Advancing AI 2026 event this week, CEO Lisa Su confirmed development of EPYC processors based on Zen 7, codenamed Florence. The news came alongside the formal launch of Zen 6-based Venice chips. But the real story lies further out.
Zen 7 Florence promises major architectural shifts. Leaks point to a potential 288-core configuration for top-tier server parts. That figure comes from a complex chiplet design. Two high-end Dwarka I/O dies. Dual Mathura memory controller dies. Eight Steamboat compute dies. Each Steamboat CCD lacks traditional on-die L3 cache. Instead it stacks a dedicated cache die underneath. The result? Seven megabytes of L3 per core. Total cache approaches two gigabytes in a fully loaded socket. Staggering density. Nearly double what current generations deliver.
Production for Florence is slated to begin in mid-2028. Launch could follow by late that year. Those dates surfaced in a detailed leak covered by HotHardware. The same report projects 15 to 25 percent instructions-per-clock gains over Zen 6. Classic cores gain built-in acceleration too. Four times the FP8 throughput per cycle. Double the INT8 performance. Such boosts matter for AI inference and training workloads that now dominate data centers.
But first, the industry digests Venice. AMD launched the sixth-generation EPYC 9006 series on July 23. These chips use TSMC’s 2nm process. Flagship models reach 256 cores in dense Zen 6c variants. Standard versions top out around 96 cores. Memory support jumps to 16 channels of DDR5. Speeds hit 12,800 MT/s. PCIe 6.0 lanes scale to 128 per socket. The platform delivers up to 70 percent better CPU performance than prior Turin parts, according to AMD’s claims.
Su highlighted these gains during her keynote. She also namedropped Florence explicitly. The processor will incorporate ACE AI extensions. Those extensions originated in the x86 Advisory Working Group, a collaboration between AMD and Intel. GCC compiler patches already exist for them. Florence adds next-generation memory technologies. MRDIMMs and LPDDR variants appear on the roadmap. Phoronix first reported Su’s confirmation of these features for the Zen 7 EPYC.
Memory and I/O upgrades matter as much as core counts. Current Turin processors support 12 memory channels at 6400 MT/s. Venice doubles that bandwidth potential. Florence will push further with advanced DIMM standards. The combination targets hyperscalers running massive AI models. Bandwidth bottlenecks have slowed progress in large language model training. AMD aims to ease those constraints.
Platform changes accompany the new chips. Venice moves to an SP7 socket. Physical dimensions grow 12 percent larger than SP5. The design accommodates more pins and power delivery. SP8 follows for later generations. It supports even higher PCIe lane counts in dual-socket setups. Details emerged last year in analysis from Wccftech. Early systems spotted at Computex already demonstrated the new memory and interconnect capabilities.
Zen 8 development runs in parallel. Su confirmed work on the architecture, codenamed Ravenna for EPYC. No specifics on timelines or features yet. The mention signals AMD’s commitment to annual cadence improvements. Past generations stretched two years or more between major jumps. Competitive pressure from Intel and custom silicon providers has changed that dynamic.
Leaked roadmaps show Florence supporting multiple configurations. Two to eight CCDs per socket. Backwards compatibility with some prior I/O dies. TDP envelopes up to 600 watts. PCIe 6.0 plus CXL 3.2. xGMI4 links at 80 Gbps. Tapeout for initial silicon occurred in October 2026 according to the Notebookcheck report on the leak. That early silicon validation sets the stage for volume manufacturing two years later.
Laptop and client derivatives also benefit. Grimlock Point APUs pair classic and dense cores on a monolithic I/O die. Efficiency gains reach 30 to 36 percent at three watts per core compared with Zen 6. Thin-and-light systems stand to see the biggest uplift. Server efficiency metrics improve 16 to 20 percent at sub-nine-watt per core loads. The same Steamboat-style cache stacking could appear in lower power variants. Desktop parts remain focused on AM5 with up to 16 cores per CCD and optional second-generation 3D V-Cache.
Market reaction mixed. Investors cheered the Venice launch and Anthropic partnership announcement. AMD committed up to $5 billion in strategic investment. The deal includes supply of MI450 GPUs and EPYC processors for Claude model training. Helios rack-scale systems pair the new CPUs with Instinct accelerators. Early deployments target 2027. Microsoft expands Azure instances based on Venice. HPE unveiled the Cray Supercomputing GX5000 with 40 percent higher core density using the new EPYC chips.
Challenges remain. TSMC’s 2nm ramp for Venice already strains capacity. Florence moves to the A14 node. That process node brings its own yield and cost questions. Power consumption at 600 watts demands advanced cooling. Data center operators weigh total cost of ownership carefully. Software optimization for the new ACE extensions will take time. Yet the core count progression tells a clear story. AMD refuses to cede ground on density.
Intel’s Xeon 6 series tops out at 144 cores in efficiency variants. Custom ARM designs from hyperscalers reach higher thread counts but lack x86 compatibility. AMD’s chiplet approach scales faster. Eight CCDs. Flexible configurations. Massive cache. The formula worked for Genoa and Turin. Florence takes it to extremes.
Analysts expect more specialization. Su hinted at broader lineups tailored for specific AI and cloud workloads. Some chips optimize for inference. Others target high-performance training. Still others focus on traditional enterprise applications. The one-size-fits-all era ended years ago. Florence accelerates that segmentation.
Recent coverage reinforces the momentum. Club386 detailed the July 2026 Venice debut and 5 GHz clock potential in certain SKUs. Microsoft leaks confirmed those high frequencies for Zen 6 EPYC parts. Overclock3D reported the news just days ago. Such single-threaded gains complement the core count story. Databases and latency-sensitive workloads benefit as much as parallel AI jobs.
So the roadmap stretches clear to 2029 and beyond. Venice ships now. Florence enters production in 2028. Ravenna follows. Each generation layers more cache, faster memory, specialized AI instructions. Data center operators face constant upgrade pressure. Stay still and fall behind. Adopt early and absorb integration costs.
AMD’s bet looks calculated. Hyperscalers need more compute immediately. Agentic AI systems multiply workloads. Traditional servers evolve into AI factories. The company that delivers balanced performance, efficiency and scalability wins the socket. For now Florence represents the next big leap. Two hundred eighty-eight cores. Two gigabytes of cache. Next-generation memory. The specifications sound almost speculative. But the confirmation came straight from Su.
Execution will decide success. Yields on the complex stacking. Software readiness for ACE. Power and thermal management at scale. Partners like HPE and ASUS already build systems around Venice. They stand ready for Florence when it arrives. The server market rarely waits. Demand for AI infrastructure grows faster than supply chains can respond.
Watch the compiler support. Watch the early silicon benchmarks. Those signals will reveal whether Florence meets the hype. Until then the industry digests Venice. And plans budgets for the 2028 refresh that could reshape data center economics once again.
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