AMD engineers have quietly added support for a distinct low-power CPU core type in the Linux kernel. The change, now queued for Linux 7.3, marks the first official recognition of a third class of x86 cores from the company. No longer will these units appear as unknown in topology reports. Instead, the operating system will classify them separately from standard performance and efficiency cores.
The patches surfaced late last month. They expand the x86 topology code to handle a new TOPO_CPU_TYPE_LOW_POWER value. Phoronix first reported the patches had been queued into the tip/tip.git x86/cpu branch. They should reach the mainline during the Linux 7.3 merge window that opens in late August. The modification itself is small. It adds roughly a dozen lines of code. Yet its implications stretch across future AMD silicon.
Current AMD heterogeneous designs already expose core types through the CPUID Fn0x80000026 EBX[31:28] leaf. Value 0 denotes performance cores. Value 1 marks efficiency cores. Value 2 now identifies low-power cores. Before these patches, Linux treated that value as unknown. User-space tools querying /sys/kernel/debug/x86/topo/cpus/* would see the mismatch. Scheduling decisions and frequency scaling could suffer as a result.
But the update goes further. On parts supporting X86_FEATURE_AMD_HTR_CORES, the kernel now routes low-power cores through amd_get_highest_perf() for boost ratio calculations. This matches the path already taken by efficiency cores. The fixed CPPC_HIGHEST_PERF_PERFORMANCE ceiling no longer applies. Such adjustments matter for accurate power management. They prevent the scheduler from overestimating capabilities on background threads.
AMD’s three-core strategy takes shape
Industry observers quickly connected the dots to Zen 6. Wccftech noted that AMD’s next architecture will field three core variants on the same ISA. Standard Zen 6 cores deliver peak performance. Zen 6C variants pack higher density with adjusted clocks and power curves. The new low-power option targets minimal consumption during idle or background workloads. Details remain sparse. One leaked configuration for the Medusa Point 1 APU shows two such Zen 6LP cores, each with 512KB L2 cache and a shared 2MB L3 slice.
That configuration hints at clever product design. Performance cores handle demanding tasks. Dense efficiency cores scale thread counts for parallel work. Low-power cores manage always-on duties. Background services. Sensor polling. OS housekeeping. They sip energy when the rest of the chip idles. The result? Better battery life in laptops. Lower thermal output in compact systems. And scheduling headaches the kernel must now address.
AMD’s approach differs from Intel’s. Intel mixes cores with distinct instruction sets. Big P-cores and little E-cores require software to handle compatibility and migration. AMD keeps the ISA consistent across all three types. The differentiation comes from microarchitecture tweaks. Power gates. Cache sizing. Frequency targets. Simpler for software. More flexible for silicon designers. Yet the scheduler still needs accurate topology data to make smart placement decisions.
Developers on X discussed early implications. One post tied the cores to rumored handheld designs. “For a real-life handheld, you want stronger cores for gaming, but lower-power cores for the OS, background tasks, sleep states, and battery life,” wrote a user analyzing the patches. Another highlighted Sony’s interest in expanding beyond the living room. While unconfirmed, the alignment feels deliberate. A handheld SoC could pair a few high-performance Zen 6 cores with a handful of low-power units. The Linux changes would let the OS direct traffic correctly from day one.
Earlier coverage captured the initial patch series. VideoCardz detailed how the low-power type stands apart from existing Zen C implementations. Zen C cores emphasize density and lower clocks within the efficiency bucket. The new low-power designation carves out a dedicated class. It signals AMD intends more granular heterogeneity in future APUs. Medusa chips, expected around CES 2027, will likely showcase the full trio.
The patches originated from AMD’s Vishal Badole. They reference the Extended CPU Topology leaf directly. Kernel.org archives hold the full series. Community review focused on the boost scaling logic and debugfs exposure. No major objections surfaced. The code is clean. The motivation clear. Future AMD platforms simply won’t work optimally without it.
Power efficiency has become table stakes. Data centers chase every watt. Mobile devices stretch battery limits. Even desktop users notice fan noise and electricity bills. AMD’s move adds another tool. Low-power cores won’t win benchmarks. They don’t need to. Their job is to vanish into the background. Literally. When the system idles, these cores keep essential functions alive at fractions of a watt.
So what comes next? More patches will follow. Scheduler tweaks for three-tier systems. Frequency domain adjustments. Perhaps user-space APIs that expose core quality beyond the current performance and efficiency labels. Linux 7.3 arrives later this year. By then, Zen 6 engineering samples should circulate. Real hardware will test these abstractions.
AMD has prepared the ground. The kernel will recognize the cores. The topology will report them correctly. Boost behavior will scale appropriately. Everything else. From thermal design to workload scheduling. Now rests on how the silicon actually performs. Early signs point to a thoughtful expansion of AMD’s hybrid playbook. One that keeps the ISA unified while diversifying power profiles. The industry will watch closely.
Recent reporting reinforced the timeline. Fudzilla emphasized the plumbing’s simplicity and its direct tie to CPUID reporting. No over-engineering. Just precise identification where it counts. That restraint speaks volumes. AMD isn’t chasing novelty. It is solving real heterogeneity challenges before products ship.
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