IBM and SUSS MicroTec Sign Agreement to Develop IBM’s Semiconductor Packaging Technology

    September 13, 2004

IBM and SUSS MicroTec today announced they have signed an agreement to develop and commercialize IBM’s next-generation, 100 percent lead-free semiconductor packaging technology, C4NP.

As part of the technology and licensing pact, SUSS MicroTec will develop a complete line of 300mm and 200mm equipment to enable commercialization of IBM’s C4NP (Controlled Collapse Chip Connection New Process), which is the first flip chip technology to offer the combined advantages of 100 percent lead-free, high reliability, fine pitch, lower material cost, as well as the flexibility to use virtually all types of solder compositions. For its part, IBM will continue advanced research and process optimization of C4NP and offer on-site process training to customers who purchase commercial systems from SUSS MicroTec.

Pioneered by IBM researchers and engineers, C4NP represents a breakthrough in wafer solder bump technology, a semiconductor packaging technique which places pre-patterned solder balls onto the surface of a chip. These bumps ultimately carry data from individual chips to the rest of a computing system via a complex arrangement of intricate wiring and materials. Chip packaging technology plays a pivotal role in how a product performs, and advances in packaging can translate into improved function.

“C4NP is an example of IBM’s commitment to semiconductor packaging technology innovation and leadership, and can fundamentally change the traditional roadmap of the industry,” Katharine Frase, vice president, Worldwide Packaging for IBM. “C4NP will enable IBM and other semiconductor manufactures to implement a 100 percent lead-free solder bumping technology as an integral part of their wafer assembly, packaging and test solution portfolios.”

Removing lead from electronic components is a global initiative for the semiconductor industry, which has examined a number of approaches to remove 100 percent of lead contained in the packaging process which connects the silicon chip to the package.

“With cost pressures on back end processing and the drive for a complete lead-free approach, C4NP is a breakthrough technology that addresses both the competitive pressures of the market as well as the demand for “green” technology providing competitive advantage to our customers,” Dr. Franz Richter, CEO SUSS MicroTec. “We are excited to collaborate with IBM and to help make available this environmentally responsible technology to the electronics industry. SUSS’ positive experience with strategic relationships such as this one allows us early entry into the high growth lead-free segment of the packaging market and further strengthens our position as a total solutions provider.”

C4NP allows the creation of pre-patterned solder balls to be completed while a wafer is still in the front-end of a manufacturing facility, potentially reducing cycle time significantly. The solder bumps can be inspected in advance and deposited onto the wafer in one simple step using technology similar to wafer-level bonding. The technology employs the simplicity of solder paste (stencil/screen), but instead uses pure molten alloy to produce the fine pitch capability of electroplating. Parallel processing allows increased efficiency and advanced quality control for wafer bumping.

C4NP also easily accommodates binary, ternary and quaternary alloys and minimizes the recurring and additive costs of consumables since only the solder balls are created and transferred to the wafer without waste. C4NP is not dependent on wafer size, allowing 200mm and 300mm wafers to be processed with similar efficiency. Additionally, C4NP has achieved technical capability well beyond the ITRS roadmap for packaging technology.

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